1. Field of the Invention
The invention relates generally to semiconductor structures. More particularly, the invention relates to semiconductor structures with enhanced performance.
2. Description of the Related Art
As semiconductor technology advances, dimensions of semiconductor devices and semiconductor structures continue to decrease. As a result of this continued scaling of semiconductor device and structure dimensions, it has become increasingly important within semiconductor technology to fabricate semiconductor devices with increasingly enhanced performance at continued decreased dimensions.
An additional trend within semiconductor technology that also provides enhanced semiconductor device performance is the fabrication of semiconductor devices upon different crystallographic orientation semiconductor substrates. Generally, particular crystallographic orientations are selected to optimize either electron mobility or hole mobility. For example, nFET devices are desirably fabricated upon {100} crystallographic planes on silicon-containing semiconductor substrates to provide enhanced electron mobility, while pFET devices are desirable fabricated upon {110} crystallographic planes on silicon-containing semiconductor substrates to provide enhanced hole mobility.
Examples of semiconductor structures fabricated using multiple crystallographic orientation substrates are known in the art.
Semiconductor device dimensions are certain to continue to decrease, and as a result thereof it is desirable to fabricate semiconductor devices with enhanced performance at decreased dimensions. To that end, additional semiconductor structures that obtain advantage through use of multiple crystallographic orientation semiconductor substrates are desirable.